Supercomputers/Systems/Armstrong (Navy DSRC)
USA · operational · hpc
Armstrong (Navy DSRC)
Also known as Navy DSRC Cray XC30 Armstrong
Operated by Navy DSRC at Navy DSRC (Stennis Space Center) .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1263 of 1345 systems have a readable citation that names them, and 56 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 514.90 TFlop/s
- Rpeak
- 761.05 TFlop/s
- Rmax ÷ Rpeak
- 67.7%
- Cores
- 38,608
- Power
- 1.08 MW
- Per watt
- 0.5 GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - Cray XC30 | Cray HPENYSE
rolls up to Hewlett Packard Enterprise | - | Reported | top500.orgweb.archive.org |
| Accelerator | - Intel Xeon Phi 5120D coprocessors, 124 nodes per Navy DSRC page | Intel | - | Reported | top500.orgweb.archive.org |
| CPU | Intel Xeon E5-2697 v2 CPUs x86-64 · 12C · 2.7 GHz · 22 nm · 130 W Intel Xeon E5-2697v2 12C 2.7GHz | Intel | - | Reported | top500.orgweb.archive.org |
| Interconnect | Cray Aries Interconnect Dragonfly · About 10 GB/s per direction · Around 1 microsecond Cray Aries interconnect | Cray HPENYSE
rolls up to Hewlett Packard Enterprise | - | Reported | top500.orgweb.archive.org |
| Operating system | Cray Linux Environment Operating systems Linux, Cray-customised · Proprietary layer over open-source Linux Cray Linux Environment | Cray HPENYSE
rolls up to Hewlett Packard Enterprise | - | Reported | top500.orgweb.archive.org |
The read
Cray XC30 at the Navy DoD Supercomputing Resource Center. TOP500 lists Intel Xeon E5-2697v2 12C 2.7GHz processors with Intel Xeon Phi 5120D coprocessors on the Aries interconnect running Cray Linux Environment, 38,608 cores, Rmax 514.90 TFlop/s, Rpeak 761.05 TFlop/s and 1,081.02 kW; it first appeared 96th on the November 2014 list and was last listed 403rd in June 2017. A Navy DSRC hardware page captured by the Internet Archive in 2015 describes Armstrong as a Cray XC30 rated at 786 TFLOPS with 1,215 standard 24-core E5-2697v2 nodes, 8 large-memory nodes and 124 Xeon Phi nodes on Cray Aries; the rating differs from TOP500's Rpeak, so the tier is reported. Named Armstrong (Navy DSRC) to distinguish it from other systems called Armstrong.
Timeline
Public list appearances
Pointers only: rank and edition, linking to the canonical entry. We do not reproduce list tables. See sourcing policy.
Site & facility
Navy DSRC (Stennis Space Center)
- Location
- Stennis Space Center, MS, USA
Change history
- 2026-10-09 Added Armstrong (Navy DSRC)
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| web.archive.org | names system and part | Intel Xeon E5-2697 v2, Cray Aries, Cray Linux Environment |
| top500.org | names system and part | Intel Xeon E5-2697 v2, Cray Aries, Cray Linux Environment |
Checked 2026-10-13 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Latency-optimised versus throughput-optimised processors, NUMA, and the end of the host-to-device copy.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.