Supercomputers/Systems/Lichtenberg I Phase 2
Germany · operational · hpc
Lichtenberg I Phase 2
Also known as Lichtenberg Phase 2 NeXtScale; TU Darmstadt HLR second stage
Operated by TU Darmstadt .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1263 of 1345 systems have a readable citation that names them, and 56 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 249.99 TFlop/s
- Rpeak
- 372.48 TFlop/s
- Rmax ÷ Rpeak
- 67.1%
- Cores
- 9,312
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - IBM NeXtScale nx360M5 system (TOP500 vendor IBM/Lenovo) | IBM | - | Reported | top500.orgtu-darmstadt.de |
| CPU | - Intel Xeon E5-2680v3 12-core 2.5 GHz, 9,312 cores in total | Intel | - | Reported | top500.org |
| Interconnect | Mellanox InfiniBand FDR Interconnect Fat tree · 56 Gb/s per 4x port · About 1 microsecond InfiniBand FDR | NVIDIA | - | Reported | top500.org |
The read
The second TOP500 entry of TU Darmstadt's first Lichtenberg high-performance computer, distinct from the Phase I iDataPlex entry recorded as Lichtenberg I and from Lichtenberg II. TOP500 lists an IBM/Lenovo NeXtScale nx360M5 system of Xeon E5-2680v3 12-core 2.5 GHz processors on InfiniBand FDR with 9,312 cores, 249.99 TFlop/s Rmax and 372.48 TFlop/s Rpeak, ranked 232nd in November 2014, 289th in June 2015 and 411th in November 2015. The university's 2013 inauguration page dates the second stage of the machine to December 2014 and says it added roughly 530 MPI nodes, four large-memory nodes and about 40 accelerator nodes, a larger count than the 388 nodes implied by TOP500's core total, so the TOP500 figures are used as listed and the tier is reported. The status date is its last list appearance.
Timeline
Public list appearances
Pointers only: rank and edition, linking to the canonical entry. We do not reproduce list tables. See sourcing policy.
Change history
- 2026-10-09 Lichtenberg I Phase 2 added from its source pages
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| top500.org | does not name this system | Mellanox InfiniBand FDR |
| tu-darmstadt.de | names system only | - |
Checked 2026-10-13 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Latency-optimised versus throughput-optimised processors, NUMA, and the end of the host-to-device copy.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.