Supercomputers/Systems/Sirius (Tsukuba)
Japan · operational · hpc
Sirius (Tsukuba)
Also known as Sirius; PACS12.0; PACS-XII
Operated by University of Tsukuba at Tsukuba Center for Computational Sciences .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1263 of 1345 systems have a readable citation that names them, and 56 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 5.63 PFlop/s
- Rpeak
- 5.95 PFlop/s
- Rmax ÷ Rpeak
- 94.6%
- Cores
- 24,192
- Power
- 113.59 kW
- Per watt
- 49.6 GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - NEC LX 401Bax-3GA system | NEC | - | Reported | top500.org |
| Accelerator | AMD Instinct MI300A Accelerators ROCm (CDNA 3) · TSMC N5/N6 · 550 W AMD Instinct MI300A APU, four per node, 24 nodes | AMD | 96 reported | Reported | ccs.tsukuba.ac.jpccs.tsukuba.ac.jp |
| CPU | AMD 4th Gen EPYC 24C (in MI300A) CPUs x86-64 · 24C · 1.8 GHz · TSMC N5 AMD 4th Gen EPYC 24-core Zen 4 CPU integrated in each MI300A | AMD | - | Reported | ccs.tsukuba.ac.jptop500.org |
| Interconnect | NVIDIA InfiniBand NDR (Quantum-2) Interconnect Fat tree or dragonfly+ · 400 Gb/s per port · Under 0.6 microseconds four 400 Gb/s InfiniBand NDR links per node | NVIDIA | - | Reported | ccs.tsukuba.ac.jpccs.tsukuba.ac.jp |
| Storage | DDN EXAScaler Storage Lustre appliance DDN EXAScaler parallel file system, 5.2 PB at 100 GB/s | DDN | - | Reported | ccs.tsukuba.ac.jp |
| Operating system | Red Hat Enterprise Linux Operating systems Linux distribution · Open source, commercial support subscription Red Hat Enterprise Linux | Red Hat | - | Reported | top500.org |
The read
Tsukuba's unified-memory supercomputer, listed by the Center for Computational Sciences as Sirius (PACS 12.0): 24 nodes, each with four AMD Instinct MI300A APUs (24-core Zen 4 CPU, CDNA 3 GPU and 128 GB HBM3 per package), four 400 Gb/s InfiniBand NDR links per node, 11.9 PFlop/s total theoretical peak, and a 5.2 PB DDN EXAScaler file system at 100 GB/s (https://www.ccs.tsukuba.ac.jp/wp-content/uploads/sites/14/2025/11/Sirius.pdf, planned for Q1 2026). TOP500 lists the NEC LX 401Bax-3GA at 5.63 PFlop/s Rmax and 5.95 PFlop/s Rpeak, with 24,192 cores and 113.59 kW during the HPL run, in 278th place in June 2026 (https://top500.org/system/180478/). Not given a list-appearance row because the June 2026 edition is already full in this dataset. It sits beside the JCAHPC Miyabi system that CCS also runs.
Timeline
- 2026 First operational source
Site & facility
Tsukuba Center for Computational Sciences
- Location
- Tsukuba, Japan
- Commissioned
- 1996
Change history
- 2026-10-09 Added Sirius (Tsukuba)
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| ccs.tsukuba.ac.jp | names system and part | AMD Instinct MI300A, NVIDIA InfiniBand NDR (Quantum-2) |
| top500.org | names system, part and count | AMD Instinct MI300A, NVIDIA InfiniBand NDR (Quantum-2) · counts: 96 |
Checked 2026-10-13 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Why accelerators exist, what the memory hierarchy costs, and how the CPU and accelerator merged onto one package.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.